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<h1>Reset Controller Interface Peripheral</h1>
<null><a name="RSTC"></a><b>RSTC</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_RSTC">AT91S_RSTC</a>)</font></i><b>  0xFFFFFD00 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_RSTC">AT91C_BASE_RSTC</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>1</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_SYS">AT91C_ID_SYS</a>)</font></i></font></td><td><font size="-1">System Peripheral</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTC_CfgPMC">AT91F_RSTC_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for RSTC</font></td></tr>
</null></table><br><br></null><a name="RSTC"></a><h2>RSTC Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_RSTC">AT91S_RSTC</a>)</font></i></h2>
<a name="RSTC"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_RSTC.html#RSTC_RCR">RSTC_RCR</a></font></td><td><font size="-1">Reset Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_RSTC.html#RSTC_RSR">RSTC_RSR</a></font></td><td><font size="-1">Reset Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM7S256_RSTC.html#RSTC_RMR">RSTC_RMR</a></font></td><td><font size="-1">Reset Mode Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTSoftReset">AT91F_RSTSoftReset</a></b></font></td><td><font size="-1">Start Software Reset</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTSetMode">AT91F_RSTSetMode</a></b></font></td><td><font size="-1">Set Reset Mode</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTIsSoftRstActive">AT91F_RSTIsSoftRstActive</a></b></font></td><td><font size="-1">Return !=0 if software reset is still not completed</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTGetStatus">AT91F_RSTGetStatus</a></b></font></td><td><font size="-1">Get Reset Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_RSTGetMode">AT91F_RSTGetMode</a></b></font></td><td><font size="-1">Get Reset Mode</font></td></tr>
</null></table></null><h2>RSTC Register Description</h2>
<null><a name="RSTC_RCR"></a><h4><a href="#RSTC">RSTC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> RSTC_RCR  <i>Reset Control Register</i></h4><ul><null><font size="-2"><li><b>RSTC</b> <i><a href="AT91SAM7S256_h.html#AT91C_RSTC_RCR">AT91C_RSTC_RCR</a></i> 0xFFFFFD00</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="RSTC_PROCRST"></a><b>RSTC_PROCRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_PROCRST">AT91C_RSTC_PROCRST</a></font></td><td><b>Processor Reset</b><br>0 = No effect.<br>1 = If KEY is correct, resets the processor.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="RSTC_PERRST"></a><b>RSTC_PERRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_PERRST">AT91C_RSTC_PERRST</a></font></td><td><b>Peripheral Reset</b><br>0 = No effect.<br>1 = If KEY is correct, resets the peripherals.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="RSTC_EXTRST"></a><b>RSTC_EXTRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_EXTRST">AT91C_RSTC_EXTRST</a></font></td><td><b>External Reset</b><br>0 = No effect.<br>1 = If KEY is correct, asserts the NRST pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="RSTC_KEY"></a><b>RSTC_KEY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_KEY">AT91C_RSTC_KEY</a></font></td><td><b>Password</b><br>Should be written at value 0xA5. Writting any other value in this field aborts the write operation.</td></tr>
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<a name="RSTC_RSR"></a><h4><a href="#RSTC">RSTC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> RSTC_RSR  <i>Reset Status Register</i></h4><ul><null><font size="-2"><li><b>RSTC</b> <i><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSR">AT91C_RSTC_RSR</a></i> 0xFFFFFD04</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="RSTC_URSTS"></a><b>RSTC_URSTS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_URSTS">AT91C_RSTC_URSTS</a></font></td><td><b>User Reset Status</b><br>0 = No high-to-low edge on NRST happened since the last read of RSTC_RSR.<br>1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_RSR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="RSTC_BODSTS"></a><b>RSTC_BODSTS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_BODSTS">AT91C_RSTC_BODSTS</a></font></td><td><b>Brownout Detection Status</b><br>0 = No brownout high-to-low transition happened since the last read of RSTC_RSR.<br>1 = At least one brownout high-to-low transition has been detected since the last read of RSTC_RSR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="RSTC_RSTTYP"></a><b>RSTC_RSTTYP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP">AT91C_RSTC_RSTTYP</a></font></td><td><b>Reset Type</b><br>Reports the cause of the last processor reset.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="RSTC_RSTTYP_POWERUP"></a><b>RSTC_RSTTYP_POWERUP</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_POWERUP">AT91C_RSTC_RSTTYP_POWERUP</a></font></td><td><br>Power-up Reset. VDDCORE rising.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="RSTC_RSTTYP_WAKEUP"></a><b>RSTC_RSTTYP_WAKEUP</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_WAKEUP">AT91C_RSTC_RSTTYP_WAKEUP</a></font></td><td><br>WakeUp Reset. VDDCORE rising.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="RSTC_RSTTYP_WATCHDOG"></a><b>RSTC_RSTTYP_WATCHDOG</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_WATCHDOG">AT91C_RSTC_RSTTYP_WATCHDOG</a></font></td><td><br>Watchdog Reset. Watchdog overflow occured.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="RSTC_RSTTYP_SOFTWARE"></a><b>RSTC_RSTTYP_SOFTWARE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_SOFTWARE">AT91C_RSTC_RSTTYP_SOFTWARE</a></font></td><td><br>Software Reset. Processor reset required by the software.</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="RSTC_RSTTYP_USER"></a><b>RSTC_RSTTYP_USER</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_USER">AT91C_RSTC_RSTTYP_USER</a></font></td><td><br>User Reset. NRST pin detected low.</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="RSTC_RSTTYP_BROWNOUT"></a><b>RSTC_RSTTYP_BROWNOUT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_RSTTYP_BROWNOUT">AT91C_RSTC_RSTTYP_BROWNOUT</a></font></td><td><br>Brownout Reset occured.</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="RSTC_NRSTL"></a><b>RSTC_NRSTL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_NRSTL">AT91C_RSTC_NRSTL</a></font></td><td><b>NRST pin level</b><br>Registers the NRST level.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="RSTC_SRCMP"></a><b>RSTC_SRCMP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_SRCMP">AT91C_RSTC_SRCMP</a></font></td><td><b>Software Reset Command in Progress.</b><br>0 = No software command is being performed. The reset controller is ready for a software command.<br>1 = A software reset command is being performed by the reset controller, the reset controller is busy.</td></tr>
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<a name="RSTC_RMR"></a><h4><a href="#RSTC">RSTC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> RSTC_RMR  <i>Reset Mode Register</i></h4><ul><null><font size="-2"><li><b>RSTC</b> <i><a href="AT91SAM7S256_h.html#AT91C_RSTC_RMR">AT91C_RSTC_RMR</a></i> 0xFFFFFD08</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="RSTC_URSTEN"></a><b>RSTC_URSTEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_URSTEN">AT91C_RSTC_URSTEN</a></font></td><td><b>User Reset Enable</b><br>0 = The detection of a low level on the pin NRST does not generate a User Reset.<br>1 = The detection of a low level on the pin NRST does not generate a User Reset.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="RSTC_URSTIEN"></a><b>RSTC_URSTIEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_URSTIEN">AT91C_RSTC_URSTIEN</a></font></td><td><b>User Reset Interrupt Enable</b><br>0 = USRTS bit in RSTC_RSR at 1 has no effect on SCIRQ.<br>1 = USRTS bit in RSTC_RSR at 1 asserts SCIRQ.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="RSTC_ERSTL"></a><b>RSTC_ERSTL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_ERSTL">AT91C_RSTC_ERSTL</a></font></td><td><b>User Reset Length</b><br>The external reset is asserted during a time of 2 power (ERSTL+1). This allows assertion duration to be programmed between 60us and 2s.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="RSTC_BODIEN"></a><b>RSTC_BODIEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_BODIEN">AT91C_RSTC_BODIEN</a></font></td><td><b>Brownout Detection Interrupt Enable</b><br>0 = BODSTS bit in RSTC_RSR at 1 has no effect on SCIRQ.<br>1 = BODSTS bit in RSTC_RSR at 1 asserts SCIRQ.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="RSTC_KEY"></a><b>RSTC_KEY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_RSTC_KEY">AT91C_RSTC_KEY</a></font></td><td><b>Password</b><br>Should be written at value 0xA5. Writting any other value in this field aborts the write operation.</td></tr>
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